Variable gain amplifiers (VGAs) are important building blocks in systems where amplification and processing of analog signals with low distortion over a high input dynamic range is required. FIG. 1 (a) shows schematically and exemplarily an amplification circuit 1 comprising a VGA 2 and an automatic gain control (AGC) loop 10 that shall ensure that only minimal distortion is introduced by the VGA over a wide dynamic range of the input. The AGC loop 10 comprises a peak detector 11, which outputs a DC signal proportional to the amplitude at the output voltage Vout of the VGA 2. The output of the peak detector 11 is compared with a desired output amplitude provided on the pin OA through an operational amplifier (OpAmp) 12 and the error signal at the output of the OpAmp 12 is used to automatically set the gain of the VGA 2 to maintain the amplitude of the output voltage Vout at a constant level, even if the input amplitude to the VGA 2 changes. When the amplification circuit 1 is embedded in a larger system, it is usually beneficial to have two switchable modes of operation: an AGC mode, in which the gain of the VGA 2 is automatically set by the
OpAmp 12 and a manual gain control mode (MGC), in which the gain can be set manually by controlling the input via the pin GC (gain control). In both modes, the output of the peak detector 11 is available through a buffer 13 on a pin PKD as an output to a peripheral system (not shown in the figure). The pin MS (mode selection) can be used to switch between the two modes through a switching circuit 14, wherein when MS is logic zero, the MGC mode is activated, and when MS is logic one, the AGC mode is activated.
A detailed view of an exemplary implementation of the switching circuit 14 is shown in FIG. 1 (b). The switching circuit 14 is formed by two complementary transmission gates and comprises a selection signal input 15 connected to the pin MS, a first signal input 16 connected to the pin GC, a second signal input 17 connected to the output of the OpAmp 12 and an output 18 connected to the gain control setting input of the VGA (VGAGC). The two complementary transmission gates comprise an inverter 19, a first pair of an NMOS transistor 20 and a PMOS transistor 21 (first transmission gate) and a second pair of an NMOS transistor 22 and a PMOS transistor 20 (second transmission gate). The first transmission gate 20, 21 is configured to allow signals to pass through from the first signal input 16 to the output 18 in response to the selection signal input 15 being driven low (logic zero) and the second transmission gate 22, 23 is configured to allow signals to pass through from the second signal input 17 to the output 18 in response to the selection signal input 15 being driven high (logic one). Thus, in the first case (MGC mode), the signal from the pin GC is available at the output 18 of the switching circuit 14, and in the second case (AGC mode), the output of the OpAmp 12 is available at the output 18 of the switching circuit 14.
Normally, in the MGC mode, the pin GC is used as an input pin, i.e., the peripheral system can write the value of the desired gain on the pin GC. However, the inventor has realized that in some peripheral systems, when the AGC mode is activated, it is also required that the value at the output of the OpAmp 12 is read out by the system.